1. Field of the Invention
The invention relates to a method of static timing analysis, and more particularly to a method for performing static timing analysis on a multi-clock logic circuit.
2. Description of the Related Art
During the development process of an integrated circuit, computer-aided design (CAD) software is frequently used to perform various analyses to verify the circuit design and examine its performance so as to improve it. The timing analysis tool is one of the CAD software widely used for predicting the performance and accuracy of the designed circuit.
Timing analysis is generally categorized into two types: dynamic timing analysis and static timing analysis (STA). The dynamic timing analysis provides the most detailed and accurate simulated results of a circuit, which take a long time to obtain. Static timing analysis, on the other hand, provides a time saving method to predict the performance of a circuit and determine if the timing of the circuit is correct according to design expectations. Static timing analysis provides not only a complete timing path validation, but also a fast way to find out the critical paths on which timing violations may occur.
FIG. 1 illustrates a circuit that is verified by using conventional static timing analysis. All the logic elements connected between a flip-flop (FF) 102 and FF 104 are represented as a combinational logic circuit 106. The FF 102 is used for receiving an input signal Input2 and a source clock signal CKs, and outputting a signal SGN1 to the combinational logic circuit 106. In addition, the combinational logic circuit 106 further receives an input signal Input1 and outputs a signal SGN2 and an output signal Output1. The FF 104 is used to receive the signal SGN2 and a destination clock signal CKd, and produces the output signal Output2.
The static timing analysis on a circuit is referred to performing a timing analysis on all signal transmission paths of the circuit from each beginning terminal to each end terminal, as well as reporting whether any one of the signal transmission paths on which timing violations occur. The beginning terminal can be an input port or clock pin, and the end terminal can be an output port or an input data terminal of the flip-flop device. In FIG. 1, four signal transmission paths are found as follows: (1) the path between the input signal Input1 and the output signal Output1, (2) the path between the input signal Input1 and the signal SGN2, (3) the path between the input signal Input2 and the output signal Output1, and (4) the path between the input signal Input2 and the signal SGN2. Static timing analysis can be used to verify whether the four signal transmission paths satisfy the timing requirement. If so, it indicates that no timing violation occur on the circuit.
However, the conventional static timing analysis tool may result in faulty results and is difficult to use when the FF's clock input terminal CK in the circuit to be analyzed has multiple options of clock signals, such as an FF 204 of a logic circuit with multiple clock signals, as shown in FIG. 2. The clock input terminal CK1 of the FF 202 receives a source clock signal CKs and clock input terminal CK2 of the FF 204 receives the clock Out. The clock Out is the output signal of a multiplexer 206. The multiplexer 206 can receive a first destination clock CKd1 and a second destination clock CKd2. The multiplexer 206, controlled by a selection signal SEL, selects either the first destination clock CKd1 or the second destination clock CKD2 as the clock Out. When performing the static timing analysis on the circuit as shown in FIG. 2, the conventional static timing analyzer possibly performs analysis on the situation with respect to one of the destination clock signals only, and ignores the situation with respect to the other destination clock signal. In this case, the critical path on which a timing violation may occur will not be found. As a result, in some situations, faulty results are produced because the potential critical path where the timing violation occur cannot be identified.
Another approach to performing static timing analysis on the circuit shown in FIG. 2 is to set case parameters in the static timing analyzer, that is, to perform a set case analysis. In other words, the user can set different cases with respect to all possible clock signals that would be received by the clock input terminals CK1 and CK2 of the FFs 202 and 204 respectively, and analyze those cases separately. If the clock input terminals CK1 and CK2 of the FFs 202 and 204 can respectively receive one of M source clock signals and one of N destination clock signals, M times N static timing analyses should be performed and the user needs to set up those cases for M by N times. In this situation, the user needs to spend a lot of time for the set case analysis, which is very inefficient use of time and is inconvenient for the user during the circuit developing process. Thus, it is desirable to have a static timing analysis approach that is efficient and easy to use for performing analysis on such circuit.